1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a multi-chip package including one or more semiconductor chips.
2. Description of the Related Art
In a general semiconductor package, one or a plurality of semiconductor chips are encapsulated with an epoxy mold compound (EMC) for protection, and are mounted on a printed circuit board (PCB).
It is desirable for electronic devices to have high speed, high capacity and high integration, as the demand for smaller and lightweight power devices as (e.g., applied to cars, industrial devices) is constantly increasing. Also, power devices also desirably have low heat generation, high heat dissipation, and high reliability. An improved multi-chip power module package in which a plurality of semiconductor chips is used in a single semiconductor package is desirable.
U.S. Pat. No. 5,703,399, assigned to Mitsubishi, discloses one type of power semiconductor module package. The semiconductor package has a structure in which a plurality of semiconductor chips constituting a power circuit and a control circuit are mounted on a lead frame. An EMC having good thermal conductivity is used at a lower portion of the lead frame, and a heat sink formed of copper (Cu) is under the lead frame and is separated slightly therefrom, so that heat generated from a power circuit chip can be effectively released to the outside.
The power semiconductor module package has the following limitations.
First, the EMC is filled between a backside of the lead frame and the heat sink of Cu in order to maintain an insulating characteristic. The EMC limits the ability of the power circuit chip to release heat to the outside of the power semiconductor module package.
Secondly, the fabrication process of the power semiconductor module package is complicated because two EMCs having different properties are used for one power semiconductor module package.
Thirdly, if a plurality of semiconductor chips is mounted on the lead frame, it is not easy to insulate the semiconductor chips from each other because of conductivity of the lead frame. Particularly, this problem becomes worse when the power semiconductor module package is used in a high-power device.
To solve the aforementioned limitations, a method of fabricating a power semiconductor module package employing an insulation substrate such as a direct bonding copper (DBC) substrate or an insulated metal substrate (IMS) substrate is being proposed.
The DBC substrate includes Cu layers respectively attached to both sides of an insulation ceramic layer, and has been known for its relatively good heat release characteristic. However, the DBC substrate is expensive to produce, because the Cu layer is partially formed according to a designed pattern.
The IMS substrate includes a polymer insulation layer formed on a top surface of an aluminum substrate, and a Cu layer formed in a pattern on the polymer insulation layer. The IMS substrate has a relatively low fabrication cost in comparison to the DBC substrate, but has a poor thermal characteristic and a poor insulation characteristic.
Therefore, it is desirable to implement a multi-chip package having an insulation structure with low thermal resistance and high electrical resistance without using the insulation substrate such as the DBC substrate or the IMS substrate.
Embodiments of the invention address the above problems, and other problems, individually and collectively.